EDN

Deriving design margins for successful timing closure

With the fast developing technology, the complexity of design is increasing day by day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and ...
EDN

Global approach to timing margins and constraint definition for SoC design, Part 1

The dependence of yield in respect to design margin is depicted in Figure 1. Below a certain level, yield is destined to be 0, because physical phenomena that occur, and may only become evident after ...