Purists may argue that you can't create true eye diagrams by using the eye-scan mode of Agilent's new 68-channel, 300/600-MHz (state), 1.2-GHz (timing)/4-GHz (timing-zoom), deep-memory logic-analysis ...
Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
At one time the boundaries between analog and digital designs were clearly defined. As the complexity and performance levels of systems have increased, maintaining those boundaries has become more ...
For designers of telecommunications and wireless products, the challenge is to choose an appropriate mix of instruments for analysis and debug, and the move is to logic and protocol analyzers.
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