EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
EDN

Detect wire breaks with unusual CMOS gate circuit

CMOS devices have large input impedance with input currents on the order of 0.01nA. Adding feedback circuitry can result in a latch-like device that can be used to store bits, and also operate in a ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
TechRepublic

Low Power With Improved Noise Margin for Domino CMOS NAND Gate

With the advancement in semiconductor technology, chip density and operating frequency are increasing, so the power consumption in VLSI circuits has become a major problem of consideration. More power ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...